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Internal Architecture

Chapter 2

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Figure 2. Cache Sector Organization

Two forms of cache misses and associated cache fills can take

place—a sector replacement and a cache line replacement. In

the case of a sector replacement, the miss is due to a tag

mismatch, in which case the required cache line is filled from

external memory, and the cache line within the sector that was

not required is marked as invalid. In the case of a cache line

replacement, the address matches the tag, but the requested

cache line is marked as invalid. The required cache line is filled

from external memory, and the cache line within the sector that

is not required remains in the same cache state.

Prefetching

The AMD-K6 processor performs cache prefetching for sector

replacements only—as opposed to cache line replacements.

This cache prefetching results in the filling of the required

cache line first, and a prefetch of the second cache line.

Furthermore, the prefetch of the cache line that is not required

is initiated only in the forward direction—that is, only if the

requested cache line is the first cache line within the sector.

From the perspective of the external bus, the two cache-line

fills typically appear as two 32-byte burst read cycles occurring

back-to-back or, if allowed, as pipelined cycles.

Predecode Bits

Decoding x86 instructions is particularly difficult because the

instructions are variable-length and can be from 1 to 15 bytes

long. Predecode logic supplies the predecode bits that are

associated with each instruction byte. The predecode bits

indicate the number of bytes to the start of the next x86

instruction. The predecode bits are stored in an extended

instruction cache alongside each x86 instruction byte as shown

in Figure 2 on page 12. The predecode bits are passed with the

instruction bytes to the decoders where they assist with parallel

x86 instruction decoding.

Tag

Address

Cache Line 1 Byte 31 Predecode Bits

Byte 30 Predecode Bits

........ ........ Byte 0 Predecode Bits

MESI Bits

Cache Line 2 Byte 31 Predecode Bits

Byte 30 Predecode Bits

........ ........ Byte 0 Predecode Bits

MESI Bits

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