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AMD-K6 Datasheet(PDF) 56 Page - Advanced Micro Devices |
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AMD-K6 Datasheet(HTML) 56 Page - Advanced Micro Devices |
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56 / 346 page ![]() 38 Software Environment Chapter 3 AMD-K6® Processor Data Sheet 20695H/0—March 1998 Preliminary Information Figure 29. Machine-Check Type Register (MCTR) Test Register 12 (TR12). Test register 12 provides a method for disabling the L1 caches. Figure 30 shows the format of TR12. Figure 30. Test Register 12 (TR12) Time Stamp Counter. W i t h e a ch proc es s o r cl ock cy cl e, t h e processor increments the 64-bit time stamp counter (TSC) MSR. Figure 31 shows the format of the TSC. Figure 31. Time Stamp Counter (TSC) 54 0 63 Reserved MCTR Reserved 42 1 0 63 C I 3 Symbol Description Bit CI Cache Inhibit Bit 3 0 63 TSC |
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