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Data Sheet

AD9656

Clock Phase Control (Register 0x16)

Bits[6:4]—Input Clock Phase Adjust

When the clock divider (Register 0x0B) is used, the applied

clock is at a higher frequency than the internal sampling clock.

Bits[6:4] determine at which phase the external clock sampling

occurs. This is only applicable when the clock divider is used.

Setting Bits[6:4] greater than Register 0x0B, Bits[2:0] is

prohibited.

Table 20. Input Clock Phase Adjust Options

Input Clock Phase Adjust,

Bits[6:4]

Number of Input Clock

Cycles of Phase Delay

000 (default)

001

010

011

100

101

110

111

JTX User Pattern (Register 0xA0 to Register 0xA7)

The pattern in these registers is output on all active lanes when

concatenation of Register 0xA0, Register 0xA2, Register 0xA4,

and Register 0xA6 is inserted before the scrambler if Register 0x61,

Bits[5:4] are set to 2. If Register 0x61, Bits[5:4] are set to 1 (a 40-bit

pattern), the concatenation of Register 0xA1, Bits[1:0] and

Resolution/Sample Rate Override (Register 0x100)

This register allows the user to downgrade the resolution and/or

the maximum sample rate (for lower power) in applications that do

not require full resolution and/or sample rate. Settings in this

(Register 0xFF) is written high.

Bits[2:0] do not affect the sample rate; they affect the maximum

sample rate capability of the ADC.

User I/O Control 2 (Register 0x101)

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 kΩ pull-down resistor

on the SDIO pin. This setting can be used to limit the loading

when many devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM

generator. This feature is used when applying an external

reference.

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