AD9656 datasheet(32/44 Pages) AD

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AD9656

Data Sheet

Digital Outputs and Timing

The AD9656 has differential digital outputs that power up by

default. The driver current is derived on chip and sets the output

current at each output equal to a nominal 4 mA. Each output

presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 600 mV p-p differential swing at

the receiver (see Figure 67). Alternatively, single-ended 50 Ω

termination can be used. When single-ended termination is

used, the termination voltage must be DRVDD/2; otherwise,

ac coupling capacitors can be used to terminate to any single-

ended voltage.

Figure 67. AC-Coupled Digital Output Termination Example

The AD9656 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common

mode of the digital output automatically biases itself to half the

supply of the receiver (that is, the common-mode voltage is 0.9 V

for a receiver supply of 1.8 V) if a dc-coupled connection is used

(see Figure 68). For receiver logic that is not within the bounds

of the DRVDD supply, use an ac-coupled connection. Place a

0.1 µF capacitor on each output pin and derive a 100 Ω

differential termination close to the receiver side.

Figure 68. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less

than six inches, and that the differential output traces be close

together and of equal lengths.

Figure 69 shows an example of the digital output data eye and time

interval error (TIE) jitter histogram and bathtub curve for the

AD9656 lane running at 6.4 Gbps.

Additional SPI options allow the user to further increase the

output driver voltage swing of all four outputs to drive longer

trace lengths (see Register 0x15 in Table 19). The power

dissipation of the DRVDD supply increases when this option is

used. See the Memory Map section for more information.

The format of the output data is twos complement by default.

To change the output data format to offset binary, see the

Memory Map section and Register 0x14 in Table 19.

Figure 69. AD9656 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations at 6.4 Gbps

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

VCM = Rx VCM

OUTPUT SWING = 600mV p-p

DIFFERENTIAL

0.1µF

RECEIVER

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

OUTPUT SWING = 600mV p-p

DIFFERENTIAL

RECEIVER

SERDOUTx+

SERDOUTx–

–0.5

0.5

UIs

PERIOD1: HISTOGRAM

350

400

450

–10

–5

TIME (ps)

300

250

200

100

150

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–100

–50

–150

150

100

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ@BER1: BATHTUB

EYE: ALL BITS OFFSET: –0.0108

ULS: 6000; 57327 TOTAL: 6000.57327

0.81 UI

Rev. 0 | Page 32 of 44

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