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AD9656

Data Sheet

JESD204B Synchronization Details

The AD9656 is a JESD204B Subclass 1 device and establishes

synchronization of the link through two control signals

(DSYSREF and DSYNC). At the system level, multiple converter

devices are aligned using a common DSYSREF and device clock

(CLK).

The synchronization process is accomplished over three phases:

code group synchronization (CGS), initial lane alignment sequence

(ILAS), and data transmission. If scrambling is enabled, the bits are

not actually scrambled until the data transmission phase, and

the CGS phase and ILAS phase do not use scrambling.

CGS Phase

In the CGS phase, the JESD204B transmit block transmits

/K28.5/ characters. The receiver (external logic device) must

find K28.5 characters in its input data stream using clock and

data recovery (CDR) techniques.

When a certain number of consecutive K28.5 characters are

detected on the link lanes, the receiver initiates a DSYSREF edge

so that the AD9656 transmit data establishes a local multiframe

clock (LMFC) internally.

The DSYSREF edge also resets any sampling edges within the

ADC to align sampling instances to the LMFC. This is important

to maintain synchronization across multiple devices.

The receiver or logic device deasserts the SYNC~ signal applied

to DSYNC, and the transmitter block begins the ILAS phase.

ILAS Phase

In the ILAS phase, the transmitter sends out a known pattern,

and the receiver aligns all lanes of the link and verifies the

parameters of the link.

The ILAS phase begins after SYNC~ has been deasserted (goes

high). The transmit block begins to transmit four multiframes.

Dummy samples are inserted between the required characters

so that full multiframes are transmitted. The four multiframes

include the following:

•

Multiframe 1: Begins with an /R/ character [K28.0] and

ends with an /A/ character [K28.3].

•

Multiframe 2: Begins with an /R/ character followed by a

/Q/ [K28.4] character, followed by link configuration

parameters over 14 configuration octets (see Table 12),

and ends with an /A/ character.

•

Multiframe 3: same as Multiframe 1.

•

Multiframe 4: same as Multiframe 1.

Table 12. 14 Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Reserved, don’t care (RES1)

Reserved, don’t care (RES2)

FCHK[7:0]

Data Transmission Phase

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:

•

If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.

•

If scrambling is enabled and the last octet of the

multiframe is equal to 0x7C, or the last octet of a frame is

equal to 0xFC.

Link Setup Parameters

The following demonstrates how to configure the AD9656

JESD204B interface. The steps to configure the output include

the following:

1. Disable the lanes before changing configuration.

2. Select one quick configuration option.

3. Configure the detailed options.

4. Check FCHK, checksum of JESD204B interface parameters.

5. Set additional digital output configuration options.

6. Reenable the lane(s).

Disable Lanes Before Changing Configuration

Before modifying the JESD204B link parameters, disable the link

and hold it in reset. This is accomplished by writing Logic 1 to

Select Quick Configuration Option

Write to Register 0x5E, the JESD204B quick configuration

configuration options and resulting JESD204B parameter values.

•

0x41 = four converters, one lane

•

0x42 = four converters, two lanes

•

0x44 = four converters, four lanes

•

0x21 = two converters, one lane

•

0x22 = two converters, two lanes

•

0x11 = one converter, one lane

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