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AD9656 Datasheet(PDF) 31 Page - Analog Devices |
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AD9656 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 44 page  Data Sheet AD9656 Figure 65. AD9656 Digital Processing of JESD204B Lanes Table 15. AD9656 JESD204B Typical Configurations JESD204B Quick Configuration Setting, Register 0x5E M (No. of Converters), Register 0x71, Bits[7:0] L (No. of Lanes), Register 0x6E, Bits[4:0] F (Octets/Frame), Register 0x6F, Bits[7:0], Read Only S (Samples/ADC/Frame), Register 0x74, Bits[4:0], Read Only HD (High Density Mode), Register 0x75, Bit[7], Read Only 0x41 4 1 8 1 0 0x42 4 2 4 1 0 0x44 4 4 2 1 0 0x22 2 2 2 1 0 0x21 2 1 4 1 0 0x11 1 1 2 1 0 Figure 66. AD9656 ADC Output Data Path Table 16. AD9656 JESD204B Frame Alignment Monitoring and Correction Replacement Characters Scrambling Lane Synchronization Character to be Replaced Last Octet in Multiframe Replacement Character Off On Last octet in frame repeated from previous frame No K28.7 Off On Last octet in frame repeated from previous frame Yes K28.3 Off Off Last octet in frame repeated from previous frame Not applicable K28.7 On On Last octet in frame equals D28.7 No K28.7 On On Last octet in frame equals D28.3 Yes K28.3 On Off Last octet in frame equals D28.7 Not applicable K28.7 Frame and Lane Alignment Monitoring and Correction Frame alignment monitoring and correction is part of the JESD204B specification. The 16-bit word requires two octets to transmit all the data. The two octets (MSB and LSB), where F = 2, make up a frame. During normal operating conditions, frame alignment is monitored via alignment characters, which are inserted under certain conditions at the end of a frame. Table 16 summarizes the conditions for character insertion, along with the expected characters under the various operation modes. If lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe. Based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replacement characters. 8B/10B ENCODER/ CHARACTER REPLACMENT SERIALIZER t . . . DSYNC± DSYSREF± VINA+ VINA– SERDOUT± A PATH ADC TEST PATTERN 16-BIT JESD204B TEST PATTERN 8-BIT ADC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 E0 E1 E2 E3 E4 E5 E6 E7 E10 E11 E12 E13 E14 E15 E16 E17 E8 E9 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E18 E19 E19 OPTIONAL SCRAMBLER 1 + x14 + x15 JESD204B TEST PATTERN 10-BIT DATA FROM ADC FRAME ASSEMBLER (ADD TAIL BITS) OPTIONAL SCRAMBLER 1 + x14 + x15 8B/10B ENCODER TO RECEIVER Rev. 0 | Page 31 of 44 |
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