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Data Sheet

AD9656

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins, as shown in Figure 58. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

Figure 58. Differential PECL Sample Clock (Up to 1 GHz)

Another option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 59. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

Figure 59. Differential LVDS Sample Clock (Up to 1 GHz)

In some applications, it is acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 µF capacitor (see

Figure 60).

Figure 60. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9656 contains an input clock divider with the ability to

divide the input clock by integer values from 1 to 8.

The AD9656 clock divider can be synchronized using the

external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the

clock divider to be resynchronized on every SYNC signal or

only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows multiple parts to have their

clock dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, can be sensitive to

clock duty cycle. Commonly, a ±5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9656 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This feature minimizes

performance degradation in cases where the clock input duty

cycle deviates more than the specified ±5% from the nominal 50%

duty cycle. Enabling the DCS function can significantly improve

noise and distortion performance for clock input duty cycles

ranging from 30% to 45% and from 55% to 70%.

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The loop has

a time constant associated with it that must be considered in

applications in which the clock rate can change dynamically. A

wait time of 1.5 µs to 5 µs is required after a dynamic clock

frequency increase or decrease before the DCS loop is relocked

to the input signal.

0Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

0Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Rev. 0 | Page 25 of 44

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