AD9656 datasheet(24/44 Pages) AD

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AD9656

Data Sheet

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or to improve thermal drift

characteristics. Figure 54 and Figure 55 show the typical drift

characteristics of the internal reference in 1.0 V mode and

1.4 V mode, respectively.

Figure 54. VREF Error vs. Temperature, Typical VREF = 1.0 V Drift

Figure 55. VREF Error vs. Temperature, Typical VREF = 1.4 V Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load. The internal buffer generates the positive and

negative full-scale references for the ADC core.

It is not recommended to leave the SENSE pin floating.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9656 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typically

ac-coupled into the CLK+ and CLK− pins via a transformer or

capacitors. These pins are biased internally and require no

external bias.

Clock Input Options

The AD9656 has a flexible clock input structure. The clock input

can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of

the type of signal used, clock source jitter is of the most

concern, as described in the Jitter Considerations section.

Figure 56 and Figure 57 show two preferred methods for clocking

the AD9656 (at clock rates up to 1 GHz prior to internal clock

divider). A low jitter clock source is converted from a single-ended

signal to a differential signal using either an RF transformer or an

RF balun.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 1 GHz, and the RF transformer

configuration is recommended for clock frequencies from 40 MHz

to 200 MHz. The Schottky diodes, across the transformer/balun

secondary winding limit clock excursions into the AD9656 to

approximately 0.8 V p-p differential (see Figure 56 and Figure 57).

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9656 while

preserving the fast rise and fall times of the signal that are

critical to achieving low jitter performance. However, the diode

capacitance has an effect on frequencies above 500 MHz. Care

must be taken in choosing the appropriate signal limiting diode.

Figure 56. Transformer-Coupled Differential Clock (Up to 200 MHz)

Figure 57. Balun-Coupled Differential Clock (Up to 1 GHz)

–7

–6

–5

–4

–3

–2

–1

–40

–15

TEMPERATURE (°C)

INTERNAL VREF = 1.0V

–8

–7

–6

–5

–4

–3

–2

–1

–40

–15

TEMPERATURE (°C)

INTERNAL VREF = 1.4V

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

0.1µF

CLOCK

INPUT

0.1µF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Rev. 0 | Page 24 of 44

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