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AD9656

Data Sheet

An on-chip, common-mode voltage reference is included in the

design and is available from the VCM pin. Bypass the VCM pin

to ground with a 0.1 µF capacitor, as described in the

Applications Information section.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9656, the input span is dependent on the reference voltage

(see Table 11).

Differential Input Configurations

There are several ways to drive the AD9656 either actively or

passively. However, optimum performance is achieved by

driving the analog inputs differentially. Using a differential

double balun configuration to drive the AD9656 provides excellent

performance and a flexible interface to the ADC for baseband

applications (see Figure 48).

For applications where SNR is a key parameter, differential

transformer coupling is the recommended input configuration

(see Figure 49) because the noise performance of most amplifiers

is not adequate to achieve the true performance of the AD9656.

Regardless of the configuration, the value of the shunt capacitor,

C, is dependent on the input frequency and may need to be

reduced or removed.

It is not recommended to drive the AD9656 inputs single-ended.

Figure 48. Differential Double Balun Input Configuration for Baseband Applications

Figure 49. Differential Transformer-Coupled Configuration for Baseband Applications

Table 11. Reference Configuration Summary

Selected Mode

SENSE Voltage (V)

Resulting VREF (V)

Resulting Differential

Span (V p-p)

Fixed Internal Reference

AGND to 0.2 V

1.0 V to 1.4 V internal, SPI selectable with

2.0 to 2.8

Programmable Internal Reference

Tie SENSE pin to external R

divider (see Figure 51)

0.5 × (1 + R2/R1), for example: R1 = 3.2 kΩ,

R2 = 5.8 kΩ for VREF = 1.4 V

2 × VREF

Fixed External Reference

AVDD

1.0 V to 1.4 V applied to external VREF pin

2.0 to 2.8

ADC

0.1µF

2V p-p

VCM

*C1

0.1µF

Ω

200

Ω

VINx+

VINx–

ET1-1-I3

5pF

*C1 IS OPTIONAL.

2V p-p

*C1

*C1 IS OPTIONAL

49.9

0.1

μF

ADT1-1WT

1:1 Z RATIO

VINx–

ADC

VINx+

*C1

VCM

Ω

200Ω

0.1µF

5pF

Rev. 0 | Page 22 of 44

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