AD9656 datasheet(30/44 Pages) AD

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AD9656

Data Sheet

Check FCHK, Checksum of JESD204B Interface Parameters

The JESD204B parameters can be verified through the checksum

value [FCHK] of the JESD204B interface parameters. Each lane has

a FCHK value associated with it. The FCHK value is transmitted

during the ILAS second multiframe and can be read from the

internal registers.

The checksum value is the modulo 256 sum of the parameters

listed in the No. column of Table 14. The checksum is calculated

by adding the parameter fields before they are packed into the

octets shown in Table 14.

The FCHK for the lane configuration for data exiting Lane 0

can be read from Register 0x78. Similarly, the FCHK for the lane

configuration for data exiting Lane 1 can be read from Register

0x79, FCHK for Lane 2 can be read from Register 0x7A, and

FCHK for Lane 3 can be read from Register 0x7B.

Table 14. JESD204B Configuration Table Used in ILAS and

CHKSUM Calculation

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Set Additional Digital Output Configuration Options

Other data format controls include the following:

•

Invert polarity of serial output data: Register 0x60, Bit 1

•

ADC data format (offset binary or twos complement):

•

Options for interpreting signal on DSYSREF and DSYNC:

•

Option to remap converter (logical lane) and SERDOUTx±

(physical lane) assignments: Register 0x82 and Register 0x83.

See Figure 64 for a simplified block diagram.

Reenable Lanes After Configuration

After modifying the JESD204B link parameters, enable the link so

that the synchronization process can begin. This is accomplished

by writing Logic 0 to Register 0x5F, Bit 0.

Figure 64. AD9656 Transmit Link Simplified Block Diagram

CONVERTER A

CONVERTER B

CONVERTER C

CONVERTER D

CROSSPOINT

SWITCH

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

SEE REGISTER

0xF5

DESCRIPTION

JESD204B

LANE CONTROL

(M = 4, L = 1, 2, 4)

LANE MUX

VINA+/

VINA–

VINB+/

VINB–

VINC+/

VINC–

VIND+/

VIND–

DSYNC+/

DSYNC–

DSYSREF+/

DSYSREF–

Rev. 0 | Page 30 of 44

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