UM0434 datasheet(362/390 Pages) STMICROELECTRONICS

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UM0434

Nexus3 module

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12.8.3

DTM operation

DTM queueing

Nexus3 implements a programmable depth queue (a minimum of 32 entries is

recommended) for queuing all messages. Messages that enter the queue are transmitted

through the auxiliary pins in the order in which they are queued.

Note:

If multiple trace messages need to be queued simultaneously, watchpoint messages have

the highest priority:

WPM

→ OTM → BTM → DTM. Up to two messages may be simultaneously queued.

Table 262.

Data trace exception summary

Exception condition

Exception handling

System reset negation

At the negation of JTAG reset (

j_trst_b), queue pointers, counters, state

machines, and registers within the Nexus3 module are reset. If data trace

is enabled, the first data trace message is a data write/read with

synchronization message.

Data trace enabled

The first data trace message (after data trace has been enabled) is a

synchronization message.

Exit from low

power/debug

Upon exit from a low-power mode or debug mode, the next data trace

message is converted to a data write/read with synchronization message.

Queue overrun

An error message occurs when a new message cannot be queued due to

the message queue being full. The FIFO discards messages until it has

completely emptied the queue. Once emptied, an error message is

queued. The error encoding indicates which type(s) of messages

attempted to be queued while the FIFO was being emptied. The next

DTM message in the queue will be a data write/read with synchronization

message.

Periodic data trace

synchronization

A forced synchronization occurs periodically after 255 data trace

messages have been queued. A data write/read with synchronization

message is queued. The periodic data trace message counter then

resets.

Event in

If the Nexus module is enabled, a

nex_evti_b assertion initiates a data

trace write/read with synchronization message upon the next data

write/read (if data trace is enabled and the EIC bits of the DC1 register

have enabled this feature).

Attempted access to

secure memory

For SOCs that implement security, any attempted read or write to secure

memory locations temporarily disables data trace and causes the

corresponding DTM to be lost. A subsequent read/write queues a data

trace read/write with a synchronization message.

Collision priority

All messages have the following priority: WPM

→ OTM → BTM → DTM.

A DTM message that attempts to enter the queue at the same time as a

watchpoint message or ownership trace message or branch trace

message will be lost. A subsequent read/write queues a data trace

read/write with a synchronization message.

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