UM0434 datasheet(363/390 Pages) STMICROELECTRONICS

363 / 390 page

Nexus3 module

UM0434

364/391

Relative addressing

The relative address feature is compliant with the

IEEE-ISTO 5001-2003 standard

recommendations and is designed to reduce the number of bits transmitted for addresses of

data trace messages. Refer to

Chapter : Relative addressing on page 357,” for details.

Data trace windowing

Data write/read messages are enabled by the RWT1

n field in the data trace control register,

DTC, for each DTM channel. Data trace windowing is achieved through the address range

defined by the DTEA and DTSA registers and by DTC[RC1

n]. All e200z3-initiated read/write

accesses that fall inside or outside these address ranges, as programmed, are candidates

to be traced.

Data Access/Instruction access data tracing

The Nexus3 module is capable of tracing both instruction access data or data access data.

Each trace window can be configured for either type of data trace by setting the DI1

n field

within the data trace control register for each DTM channel.

e200z3 bus cycle special cases

Note:

For a misaligned access that crosses a 64-bit boundary, the access is broken into two

accesses. If both accesses are within the data trace range, two DTMs are sent: one with a

size encoding indicating the size of the original access, that is, word, and one with a size

encoding for the portion that crossed the boundary, that is, 3 bytes See Table 109: Invalid

instruction forms on page 123 for examples of misaligned accesses.

Note:

An STM (store) to the cache’s store buffer within the data trace range initiates a DTM

message. If the corresponding memory access causes an error, a checkstop condition

occurs. The debug/development tool should use this indication to invalidate the previous

DTM.

Table 263.

e200z3 bus cycle cases

Special case

Action

e200z3 bus cycle aborted

Cycle ignored

e200z3 bus cycle with data error (TEA)

Data trace message discarded

e200z3 bus cycle completed without error

Cycle captured and transmitted

e200z3 (AHB) bus cycle initiated by Nexus3

Cycle ignored

e200z3 bus cycle is an instruction fetch

Cycle ignored

e200z3 bus cycle accesses misaligned data (across

64-bit boundary)—both first and second transactions

within data trace range

First and second cycle captured and two

DTMs transmitted

e200z3 bus cycle accesses misaligned data (across

64-bit boundary)—first transaction within data trace

range; second transaction out of data trace range

First cycle captured and transmitted; second

cycle ignored

e200z3 bus cycle accesses misaligned data (across

64-bit boundary)—first transaction out of data trace

range; second transaction within data trace range

First cycle ignored; second cycle captured

and transmitted

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