UM0434 datasheet(371/390 Pages) STMICROELECTRONICS

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Nexus3 module

UM0434

372/391

nex_rdy_b pin, nex_evto_b pin, and one clock output pin, nex_mcko. The output pins are

synchronized to the Nexus3 output clock,

nex_mcko.

All Nexus3 input functionality is controlled through the JTAG/OnCE port, in compliance with

IEEE 1149.1. (See

Chapter 12.5: Nexus3 register access through JTAG/OnCE on

page 348,” for details.) The JTAG pins are incorporated as I/O to the e200z3 processor and

are further described in

Chapter 11.5.2: JTAG/OnCE signals on page 308.”

The auxiliary pins are used to send and receive messages and are described in

Table 271.

Table 270.

JTAG pins for Nexus3

JTAG pin

I/O

Description of JTAG pins (included in e200z3 Nexus1)

j_tdo

Test data output.

j_tdo is the serial output for test instructions and data. It

is three-statable and is actively driven in the shift-IR and shift-DR

controller states. It changes on the falling edge of

j_tclk.

j_tdi

Test data input.

j_tdi receives serial test instruction and data. TDI is

sampled on the rising edge of

j_tclk.

j_tms

Test mode select. Input pin used to sequence the OnCE controller state

machine.

j_tms is sampled on the rising edge of j_tclk.

j_tclk

Test clock. Input pin used to synchronize the test logic and control register

access through the JTAG/OnCE port.

j_trst_b

Test reset. Input pin used to asynchronously initialize the JTAG/OnCE

controller.

Table 271.

Nexus3 auxiliary pins

Auxiliary pin

I/O

Description of auxiliary pins

nex_mcko

Message clock out. A free running output clock to development tools

for timing of

nex_mdo[n:0] and nex_mseo_b[1:0] pin functions.

nex_mcko is programmable through the DC1 register.

nex_mdo[n–0]

Message data out. Used for OTM, BTM, and DTM. External latching

nex_mdo[n:0] occurs on the rising edge of the Nexus3 clock

(

nex_mcko).

nex_mseo_b[1–0]

Message start/end out. Indicate when a message on the

nex_mdo[n:0] pins has started, when a variable length packet has

ended, and when the message has ended. External latching of

nex_mseo_b[1–0] occurs on the rising edge of the Nexus3 clock

(

nex_mcko). One- or two-pin MSEO functionality is determined at

integration time according to the SOC implementation

nex_rdy_b

Ready. Used to indicate to the external tool that the Nexus block is

ready for the next read/write access. If Nexus is enabled, this signal is

asserted upon successful completion (without error) of an AHB

system bus transfer (Nexus read or write) and is held asserted until

the JTAG/OnCE state machine reaches the capture_dr state. Upon

exit from system reset or if Nexus is disabled,

nex_rdy_b remains de-

asserted.

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