UPD17015 datasheet(52/120 Pages) NEC

52 / 120 page

µPD17015

11.2.2

Functions

The input switching block and programmable divider select the input pin and division method to be used by the

PLL frequency synthesizer.

Either the VCOH or VCOL pin can be selected as the input pin.

The selected pin will have an intermediate potential (about half of VDD).

The input to the pin is provided by an AC amplifier. The DC element should be eliminated from the input signal

by connecting a capacitor in series with the pin.

As the division method, either direct division or pulse swallow can be selected.

The programmable divider divides the signal input by means of the selected division method, using the division

ratio set by the swallow counter and programmable counter.

Table 11-1 lists the division methods and input pins (VCOH and VCOL pins) to be used.

The input pin and division method to be used are selected according to the PLLMD0 and PLLMD1 flags of the

PLL mode select register.

Fig. 11-3 shows the configuration of the PLL mode select register, together with its functions.

The division ratio of the programmable divider is set by the PLL data register via data buffers.

Section 11.2.3 describes the programmable divider and PLL data register.

Table 11-1 Input Pins and Division Methods

Division method

Pin used

Input frequency

Input amplitude

Possible division ratio

Division ratio that can be

range (MHz)

(Vp-p)

set in the data buffers

Direct division

VCOL

0.5 to 8

0.2

16 to 212 – 1

010

×H - FFF×H

(MF)

(

×: Don’t care about

low-order 4 bits.)

Pulse swallow

VCOL

6 to 55

0.2

256 to 216 – 1

0100H-FFFFH

(HF)

Pulse swallow

VCOH

40 to 220

0.2

256 to 216 – 1

0100H-FFFFH

(VHF)

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