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UPD17015 Datasheet(PDF) 64 Page - NEC |
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UPD17015 Datasheet(HTML) 64 Page - NEC |
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64 / 120 page ![]() 64 µPD17015 (5) PLL data setting example The data to be set to receive an FM band broadcast station is shown below. Receiving frequency : 100.0 MHz (FM band) Reference frequency : 25 kHz Intermediate frequency : +10.7 kHz Division value N is: N = fVCOH = 100.0 + 10.7 = 4428 (decimal) fr 0.025 = 114CH (hexadecimal) Data is written into the PLL data and PLL mode selection registers as follows: PLLR 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 11 4 C 11.7 STATE AT RESET 11.7.1 At Power-On Reset Since the PLL mode selection register is initialized to 0000B, the PLL disabled state is set. 11.7.2 At Clock-Stop The PLL disabled state is set at the time the CE pin drops to low level. 11.7.3 At CE Reset (1) CE reset caused by clock stop Since clock-stop initializes the PLL mode selection register to 0000B, the PLL disabled state is set. (2) CE reset when clock not stopped Since the PLL mode selection register retains its previous state, the previous state is set when the CE pin rises to high level. 11.7.4 During the Halt State If the CE pin is high level, the set state is held. PLLMD 1 0 1 1 VHF, 25 kHz |
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