UPD17015 datasheet(83/120 Pages) NEC

83 / 120 page

µPD17015

14.3

CLOCK-STOP FUNCTION

The clock-stop function stops the 75-kHz crystal oscillation circuit (clock stopped state) by executing a “STOP s”

instruction.

The supply current is reduced by up to 3

µA.

Specify “0000B” at operand “s” of the “STOP s” instruction.

The “STOP s” instruction is valid only when the CE pin is low level. If a “STOP s” instruction is executed while

the CE pin is high level, it is executed as a “NOP” instruction. Always execute a “STOP s” instruction when the CE

pin is low level.

The clock-stop state is released by raising the CE pin from low level to high level (CE reset).

14.3.1

Clock-Stop State

Since the crystal oscillation circuit is stopped in the clock-stop state, operation of the CPU, peripheral hardware,

and other devices is stopped.

For a description of operation of the CPU and each item of peripheral hardware, see Section 14.4.

14.3.2

Clock-Stop State Release

The clock-stop state can be released with the two methods described below. For both methods, after the clock-

stop state is released, the program starts from address 0000H.

Raising the CE pin from low level to high level (CE reset)

Dropping VDD to 1.8 V or less, then raising it to 1.8 V or more (TA = –10 to +50

°C).

Caution The power-on clear voltage varies with the CPU operating temperature. For details, see Section

15.2.

14.3.3

Clock-Stop Release by CE Reset

Fig. 14-3 shows the clock-stop release by CE reset.

UPD17015 Datasheet(PDF) 83 Page - NEC