UPD17015 datasheet(95/120 Pages) NEC

95 / 120 page

µPD17015

15.3

CE RESET

CE reset is executed by raising the CE pin from low level to high level.

When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization with

the rising edge of the pulse used for the next setting of the BTM0CY flag.

When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some

peripheral control registers to their initial value and executes the program from address 0000H.

For the initial values, see the relevant item.

CE reset operation is different when clock-stop is used and when it is not used.

15.3.1

CE Reset When Clock-Stop (STOP s Instruction) Not Used

Fig. 15-4 shows the reset operation when clock-stop is not used.

When clock-stop (STOP s instruction) is not used, the CE pin becomes high level. Then, RESET signal is output,

and reset is applied at the rising edge of the selected pulse (125 ms) used for setting the BTM0CY flag.

Fig. 15-4 CE Reset Operation When Clock-Stop Not Used

3.0 V

0 V

Normal operation

Normal

operation

XOUT

VDD

BTM0CY flag

set pulse

IRES

RES

RESET

CE reset is applied at the rising edge

of the pulse used for setting the BTM0CY

flag.

This period, t, varies with the timing when

the CE pin signal rises. It falls in the range

from 0 to 125 ms (0 < t < 125 ms), which is

the selected set time of the BTM0CY flag.

The program continues to run during this

period.

UPD17015 Datasheet(PDF) 95 Page - NEC