UPD17015 datasheet(91/120 Pages) NEC

91 / 120 page

µPD17015

15. RESET

The reset function is used to initialize device operation.

15.1

OUTLINE OF RESET FUNCTION

Fig. 15-1 outlines the reset block.

To reset a device, apply one of the following methods, as necessary.

Power-on reset : Reset by applying supply voltage VDD

CE reset

: Reset with the CE pin

Power-on reset is applied when VDD rises from a certain voltage.

CE reset is applied when the level of the CE pin goes from low to high.

The main differences between power-on reset and CE reset are the initial values of the peripheral control register

and the operation of the power failure detection circuit, as described in Section 15.5.

Power-on reset and CE reset are controlled by the reset signals (IRES, RES, or RESET signal) output from the

reset control circuit shown in Fig. 15-1.

Table 15-1 indicates the relationship between the internal reset signal and each reset.

Fig. 15-1 Outline of the Reset Block

IRES

RESET

RES

OUT

Power failure detection block

Timer block

Frequency

divider

BTM0CY flag read

Basic timer 0

STOP s

instruction

Basic timer 0 carry

disable flip-flop

Voltage

detection

circuit

Rising edge

detection

circuit

Power-on clear signal (POC)

Reset

control circuit

STOP instruction

Forced halt of release

by BTM0CY flag

Peripheral control register

System register

Stack

Program counter

Table 15-1 Relationship Between Internal Reset Signal and Each Reset

Output signal

Internal reset signal

At CE reset

At power-

At clock-stop

Contents controlled by each reset signal

on reset

IRES

Forces the device into the halt state.

The halt state is released by the setting of the

BTM0CY flag.

RES

Initializes some peripheral control registers.

RESET

Initializes the program counter, stack, system

UPD17015 Datasheet(PDF) 91 Page - NEC

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