UPD17015 datasheet(96/120 Pages) NEC

96 / 120 page

µPD17015

15.3.2

CE Reset When Clock-Stop (STOP s Instruction) Used

Fig. 15-5 shows the reset operation when clock-stop is used.

When clock-stop is used, the IRES, RES and RESET signals are output at the time the “STOP s” instruction is

executed.

Since the IRES signal is output continuously while the CE pin is low level, release by the BTM0CY flag is forcibly

halted.

Since the clock itself stops, the device stops operating.

When the CE pin rises to high level, the clock-stop state is released and oscillation begins.

The IRES signal halts release by the BTM0CY flag. When the pulse used for setting the BTM0CY flag rises after

the CE pin rises, the halt state is released and the program starts from address 0.

Fig. 15-5 CE Reset Operation When Clock-Stop Used

3.0 V

0 V

Normal operation

Clock-stop state

XOUT

VDD

BTM0CY flag

set pulse

IRES

RES

RESET

CE reset

Program starts from address 0.

Clock stop release

Oscillation start

STOP s instruction

Halt state

125 ms

15.3.3

Cautions at CE Reset

When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction

being executed.

(1) Time required for clock and other timer processing

When writing a clock program by using basic timer 0 and basic timer 1 interrupts, the program must end processing

within a certain time.

For details, see Section 10.2.5.

(2) Processing of data, flags, etc. used in the program

Care must be exercised when rewriting the contents of data, flags, etc. that cannot be processed by one instruction

so that the contents do not change even when CE reset is applied.

Examples are given below:

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