UPD17015 datasheet(72/120 Pages) NEC

72 / 120 page

µPD17015

13.5

COMMON SIGNAL AND SEGMENT SIGNAL OUTPUT WAVEFORMS

Fig. 13-7 shows sample waveforms for common signal and segment signal output.

The

µPD17015 outputs signals at a frame frequency of 62.5 Hz when driving at a 1/4 duty cycle and 1/2 bias (voltage

averaging method).

The common signals output from pins COM0 to COM3 have a relative phase difference of 1/8 and three voltage

levels (VLCD0, VLCD1, and VDD). The middle voltage level VLCD1 of the output common signals increases or decreases

by 1/2 VDD. This display method is referred to as the 1/2-bias driving method.

Each segment signal output pin outputs the segment signal with two voltage levels (0 and VDD) and phases

corresponding to the display segments. As shown in Fig. 13-7, a single segment pin is used for four display segments

(A, B, C, and D). Each segment pin can output 16 different combinations of phases, corresponding to the turning

on and off of the display segments.

A display segment is lit when the voltage difference between the common signal and segment signal is VDD.

The display segments are turned on in 1/4 duty cycles at a frequency of 62.5 Hz.

This is referred to as the 1/4-duty display method. The frequency is referred to as the frame frequency.

UPD17015 Datasheet(PDF) 72 Page - NEC