UPD17015 datasheet(53/120 Pages) NEC

53 / 120 page

µPD17015

Fig. 11-3 Configuration and Functions of the PLL Mode Select Register

6BH

R/W

Read/write

Address

Hold

Clock-stop

Power-on

1 kHz

3 kHz

5 kHz

25 kHz

Sets the division method used by the PLL frequency synthesizer.

Disables pins VCOL and VCOH

Selects pulse swallow (VCOH pin, VHF mode).

Selects pulse swallow (VCOL pin, HF mode).

Selects direct division (VCOL pin, MF mode).

Name

Flag symbol

PLL mode select register

Sets reference frequency fr of the PLL frequency synthesizer.Note

Note

For details of the reference frequency, see Section 11.3.

Items (1) to (4), below, outline the division methods:

(1) Direct division (MF)

The VCOL pin is used.

The VCOH pin enters the floating state.

In direct division, the signal input is divided according to the programmable counter only.

(2) Pulse swallow (HF)

The VCOL pin is used.

The VCOH pin enters the floating state.

When using pulse swallow, the signal input is divided according to the settings of the swallow counter and

programmable counter.

(3) Pulse swallow (VHF)

The VCOH pin is used.

The VCOL pin enters the floating state.

When using pulse swallow, the signal input is divided according to the settings of the swallow counter and

programmable counter.

UPD17015 Datasheet(PDF) 53 Page - NEC