UPD17015 datasheet(92/120 Pages) NEC

92 / 120 page

µPD17015

15.2

POWER-ON RESET

Power-on reset is executed by raising VDD from a certain voltage (called the power-on clear voltage) or less.

When VDD is less than the power-on clear voltage, the power-on clear signal (POC) is output from the voltage

detection circuit shown in Fig. 15-1.

When the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating.

While the power-on clear signal is being output, the IRES, RES and RESET signals are output.

When VDD exceeds the power-on clear voltage, the power-on clear signal is dropped and crystal oscillation starts.

At the same time, the IRES, RES and RESET signals are also dropped.

Since the IRES signal halts release by the BTM0CY flag, power-on reset is applied at the rising edge of the next

BTM0CY flag setting signal.

This operation is shown in Fig. 15-2.

At power-on reset, the program counter, stack, system register and control registers are initialized when the power-

on clear signal is output. For the initial values, see the relevant items.

In the CPU operation and clock-stop state, the power-on clear voltage is 1.8 V (rated value).

Caution The power-on clear voltage varies with the CPU operating temperature, as follows:

TA = –10 to +50

°C: 1.8 V

TA = –20 to +50

°C: 1.9 V

Fig. 15-2 Power-On Reset Operation

3.0 V

0 V

Normal operation

Device operation stopped

XOUT

VDD

BTM0CY flag

set pulse

IRES

RES

RESET

Power-on reset

Program starts from address 0

Power-on clear signal

Power-on clear release

Oscillation start

Halt state

125 ms

Power-on clear voltage

UPD17015 Datasheet(PDF) 92 Page - NEC