UPD17015 datasheet(84/120 Pages) NEC

84 / 120 page

µPD17015

Fig. 14-3 Clock-Stop Release by CE Reset

3.0 V

0 V

VDD

CE pin

XOUT pin

STOP s instruction

Approx. 125 ms

Program starts at address 0

(CE reset)

3.0 V

0 V

VDD

CE pin

XOUT pin

If a clock-stop instruction is not used, operation is as follows:

0-tSET

Program starts at address 0

(CE reset)

CE reset is applied in synchronization

with the setting of the BTM0CY flag

after the CE pin has been raised to high level.

14.3.4

Clock-Stop Release by Power-On Reset

Fig. 14-4 shows the clock-stop release by power-on reset.

If the clock-stop state is released by power-on reset, the power failure detection circuit operates.

Fig. 14-4 Clock-Stop Release by Power-On Reset (TA = –10 to +50

°C)

3.0 V

0 V

VDD

CE pin

XOUT pin

STOP s instruction

Approx. 125 ms

Program starts at address 0

(power-on reset)

3.0 V

0 V

VDD

CE pin

XOUT pin

If a clock-stop instruction is not used, operation is as follows:

Approx. 125 ms

Program starts at address 0

(power-on reset)

Oscillation stopped

1.8 V

UPD17015 Datasheet(PDF) 84 Page - NEC

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