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UPD17015 Datasheet(PDF) 8 Page - NEC |
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UPD17015 Datasheet(HTML) 8 Page - NEC |
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8 / 120 page ![]() 8 µPD17015 1. PIN FUNCTIONS 1.1 PIN FUNCTIONS Function 3-bit input port. 4-bit CMOS output port 1-bit general-purpose output port and BEEP signal output • P0D0 • 1-bit output port • BEEP • 3-kHz BEEP output 2-bit I/O and output ports • P0A0, P0A1 • 2-bit I/O port • Input or output mode can be specified in units of bits. • P0A2, P0A3 • 2-bit output port Input pin for the µPD17015 operation selection and reset signal Pins for connecting the crystal (75 kHz) for system clock oscillation. Load capacity: CI = 12 pF, CO = 33 pF Main power supply pin The pin supplies a voltage of 1.8 to 3.6 V (TA = –10 to +50 °C) to enable all functions. Note that the voltage applied to each of the other pins must not exceed the voltage applied to the VDD pin. Ground pin Output from the charge pump of the PLL frequency synthesizer. Output pin for the PLL voltage regulator. Connect this pin to GND through a 0.1- µF capacitor. Local PLL oscillator frequency input Output type Input with a pull- down resistor CMOS push-pull CMOS push-pull CMOS push-pull — CMOS push-pull (XOUT) — — CMOS tristate output — — Pin No. 37 38 1 2 | 5 6 7 | 10 11 12 13 14 15 16 17 18 19 Symbol P0B0 | P0B2 P0C0 | P0C3 P0D0/ BEEP P0A0 | P0A3 CE XOUT XIN VDD GND EO VREG VCOH VCOL At power-on reset Input Low-level output Low-level output Input (P0A0, P0A1) Low-level output (P0A2, P0A3) Input — — — Floating — Floating VREG (17) 0.1 F µ 5 |
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