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AM3874 Datasheet(PDF) 238 Page - Texas Instruments

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Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 238 Page - Texas Instruments

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AM3874, AM3871
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
8.7
General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register controls the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt generation
modes. The GPIO peripheral provides generic connections to external devices.
The device contains four GPIO modules and each GPIO module is made up of 32 identical channels.
The device GPIO peripheral supports the following:
•
Up to 128 1.8-V/3.3-V GPIO pins, GP0[0:31], GP1[0:31], GP2[0:31], and GP3[0:31] (the exact number
available varies as a function of the device configuration). Each channel can be configured to be used
in the following applications:
–
Data input/output
–
Keyboard interface with a de-bouncing cell
–
Synchronous interrupt generation (in active mode) upon the detection of external events (signal
transitions and/or signal levels).
•
Synchronous interrupt requests from each channel are processed by four identical interrupt generation
sub-modules to be used independently by the ARM or Media Controller. Interrupts can be triggered by
rising and/or falling edge, specified for each interrupt-capable GPIO signal.
•
Shared registers can be accessed through "Set and Clear" protocol. Software writes 1 to
corresponding bit position or positions to set or to clear the GPIO signal. This allows multiple software
processes to toggle GPIO output signals without critical section protection (disable interrupts, program
GPIO, re-enable interrupts, to prevent context switching to another process during GPIO
programming).
•
Separate input/output registers.
•
Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can
be toggled by direct write to the output register.
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic to be implemented.
For more detailed information on GPIOs, see the General-Purpose I/O (GPIO) Interface chapter of the
AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).
8.7.1
GPIO Peripheral Register Descriptions
Table 8-30. GPIO Registers
HEX ADDRESS
GPIO0
GPIO1
GPIO2
GPIO3
ACRONYM
REGISTER NAME
0x4803 2000
0x4804 C000
0x481A C000
0x481A E000
GPIO_REVISION
GPIO Revision
0x4803 2010
0x4804 C010
0x481A C010
0x481A E010
GPIO_SYSCONFIG
System Configuration
0x4803 2020
0x4804 C020
0x481A C020
0x481A E020
GPIO_EOI
End of Interrupt
0x4803 2024
0x4804 C024
0x481A C024
0x481A E024
GPIO_IRQSTATUS
Status Raw for Interrupt 1
_RAW_0
0x4803 2028
0x4804 C028
0x481A C028
0x481A E028
GPIO_IRQSTATUS
Status Raw for Interrupt 2
_RAW_1
0x4803 202C
0x4804 C02C
0x481A C02C
0x481A E02C
GPIO_IRQSTATUS
Status for Interrupt 1
_0
0x4803 2030
0x4804 C030
0x481A C030
0x481A E030
GPIO_IRQSTATUS
Status for Interrupt 2
_1
0x4803 2034
0x4804 C034
0x481A C034
0x481A E034
GPIO_IRQSTATUS
Enable Set for Interrupt 1
_SET_0
0x4803 2038
0x4804 C038
0x481A C038
0x481A E038
GPIO_IRQSTATUS
Enable Set for Interrupt 2
_SET_1
238
Peripheral Information and Timings
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: AM3874 AM3871



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