AM3874 datasheet(244/361 Pages) TI

244 / 361 page

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

www.ti.com

8.8.2

GPMC Electrical Data/Timing

8.8.2.1

GPMC/NOR Flash Interface Synchronous Mode Timing (Non-Multiplexed and Multiplexed Modes)

Table 8-34. Timing Requirements for GPMC/NOR Flash Interface - Synchronous Mode

(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)

(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)

OPP100/120/166

NO.

UNIT

MIN

MAX

tsu(DV-CLKH)

Setup time, read GPMC_D[15:0] valid before GPMC_CLK high

th(CLKH-DV)

Hold time, read GPMC_D[15:0] valid after GPMC_CLK high

tsu(WAITV-CLKH)

Setup time, GPMC_WAIT[x] valid before GPMC_CLK high

th(CLKH-WAITV)

Hold time, GPMC_WAIT[x] valid after GPMC_CLK high

Table 8-35. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash

Interface - Synchronous Mode

(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)

(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)

OPP100/120/166

PARAMETER

UNIT

MIN

MAX

tc(CLK)

Cycle time, output clock GPMC_CLK period

20(1)

tw(CLKH)

Pulse duration, output clock GPMC_CLK high

0.5P(2)

tw(CLKL)

Pulse duration, output clock GPMC_CLK low

0.5P(2)

td(CLKH-nCSV)

Delay time, GPMC_CLK rising edge to GPMC_CS[x] transition

F - 3(3)

F + 6(3)

td(CLKH-nCSIV)

Delay time, GPMC_CLK rising edge to GPMC_CS[x] invalid

E - 3(4)

E + 6(4)

MUX0 and Non-Multi

B - 6(5)

B + 6(5)

Muxed pins

MUX1 for

B - 10(5)

B + 6(5)

Delay time, GPMC_A[27:0] address bus valid to

GPMC_A[15:0]

td(ADDV-CLK)

GPMC_CLK first edge

MUX1/2 for

B - 10(5)

B + 6(5)

GPMC_A[27:20]

GPMC_AD[15:0]

B - 10(5)

B + 6(5)

MUX0 and Non-Multi

-3

Muxed pins

MUX1 for

-6

Delay time, GPMC_CLK rising edge to GPMC_A[27:0] GPMC_A[15:0]

td(CLKH-ADDIV)

GPMC address bus invalid

MUX1/2 for

-6

GPMC_A[27:20]

GPMC_AD[15:0]

-6

td(nBEV-CLK)

Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CLK first edge

B - 3(5)

B + 3(5)

(1)

Sync mode can operate at 50 MHz max.

(2)

P = GPMC_CLK period.

(3)

For nCS falling edge (CS activated):

•

For GpmcFCLKDivider = 0:

F = 0.5 * CSExtraDelay * GPMC_FCLK

•

For GpmcFCLKDivider = 1:

F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are

even)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise

•

For GpmcFCLKDivider = 2:

F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)

F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)

(4)

For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(5)

B = ClkActivationTime * GPMC_FCLK

244

Peripheral Information and Timings

Submit Documentation Feedback

Product Folder Links: AM3874 AM3871

AM3874 Datasheet(PDF) 244 Page - Texas Instruments

AM3874 Datasheet(HTML) 244 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL