AM3874 datasheet(303/361 Pages) TI

303 / 361 page

Rtt

Vtt

Rcp

Cac

DDR_1V5

0.1 µF

AM3874, AM3871

www.ti.com

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

8.13.4.2.4.11.9 CK and ADDR/CTRL Routing, One DDR3 Device

Figure 8-72 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-73

shows the corresponding ADDR_CTRL routing.

Figure 8-72. CK Routing for One DDR3 Device

Figure 8-73. ADDR_CTRL Routing for One DDR3 Device

8.13.4.2.4.12 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point-to-point, so its

definition is simple.

Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is

better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure

there are nearby ground vias to allow the return currents to transition between reference planes if both

reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the

return currents to transition between reference planes if one of the reference planes is ground. The goal is

to minimize the size of the return current loops.

Peripheral Information and Timings

303

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AM3874 Datasheet(PDF) 303 Page - Texas Instruments