AM3874 datasheet(307/361 Pages) TI

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AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

Table 8-75. CK and ADDR_CTRL Routing Specification(1)(2) (continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Center-to-center CK to other DDR3 trace spacing(9)

Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(9)

CK center-to-center spacing(11)

(12)

CK spacing to other net(9)

Rcp(13)

Zo-1

Zo+

Rtt(13)(14)

Zo-5

Zo+5

(9)

Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-

ended impedance, Zo.

(13) Source termination (series resistor at driver) is specifically not allowed.

(14) Termination values should be uniform across the net class.

8.13.4.2.4.13.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four

DQLMs, DQLM0–DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0–DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length

matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the MPU and the DDR3 memories, the maximum possible

Manhattan distance can be determined given the placement. Figure 8-80 shows this distance for four

loads. It is from this distance that the specifications on the lengths of the transmission lines for the data

bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-76.

Peripheral Information and Timings

307

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