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AM3874 Datasheet(PDF) 310 Page - Texas Instruments

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Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 310 Page - Texas Instruments

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AM3874, AM3871
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
Table 8-77. McASP0/1/2/3/4/5 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
MCASP0
MCASP1
MCASP2
MCASP3
MCASP4
MCASP5
0x4803 8020
0x4803 C020
0x4805 0020
0x4A1A 2020
0x4A1A 8020
0x4A1A E020
PDCLR
Pin Data Clear
(Alternate Write Address
PDOUT)
0x4803 8044
0x4803 C044
0x4805 0044
0x4A1A 2044
0x4A1A 8044
0x4A1A E044
GBLCTL
Global Control
0x4803 8048
0x4803 C048
0x4805 0048
0x4A1A 2048
0x4A1A 8048
0x4A1A E048
AMUTE
Mute Control
0x4803 804C
0x4803 C04C
0x4805 004C 0x4A1A 204C 0x4A1A 804C
0x4A1A
LBCTL
Loop-Back Test Control
E04C
0x4803 8050
0x4803 C050
0x4805 0050
0x4A1A 2050
0x4A1A 8050
0x4A1A E050
TXDITCTL
Transmit DIT Mode Control
0x4803 8060
0x4803 C060
0x4805 0060
0x4A1A 2060
0x4A1A 8060
0x4A1A E060
GBLCTLR
Alias of GBLCTL containing
only receiver reset bits;
allows transmit to be reset
independently from receive
0x4803 8064
0x4803 C064
0x4805 0064
0x4A1A 2064
0x4A1A 8064
0x4A1A E064
RXMASK
Receiver Bit Mask
0x4803 8068
0x4803 C068
0x4805 0068
0x4A1A 2068
0x4A1A 8068
0x4A1A E068
RXFMT
Receive Bitstream Format
0x4803 806C
0x4803 C06C
0x4805 006C 0x4A1A 206C 0x4A1A 806C
0x4A1A
RXFMCTL
Receive Frame Sync Control
E06C
0x4803 8070
0x4803 C070
0x4805 0070
0x4A1A 2070
0x4A1A 8070
0x4A1A E070
ACLKRCTL
Receive Clock Control
0x4803 8074
0x4803 C074
0x4805 0074
0x4A1A 2074
0x4A1A 8074
0x4A1A E074
AHCLKRCTL High Frequency Receive
Clock Control
0x4803 8078
0x4803 C078
0x4805 0078
0x4A1A 2078
0x4A1A 8078
0x4A1A E078
RXTDM
Receive TDM Slot 0-31
0x4803 807C
0x4803 C07C
0x4805 007C 0x4A1A 207C 0x4A1A 807C
0x4A1A
EVTCTLR
Receiver Interrupt Control
E07C
0x4803 8080
0x4803 C080
0x4805 0080
0x4A1A 2080
0x4A1A 8080
0x4A1A E080
RXSTAT
Status Receiver
0x4803 8084
0x4803 C084
0x4805 0084
0x4A1A 2084
0x4A1A 8084
0x4A1A E084 RXTDMSLOT Current Receive TDM Slot
0x4803 8088
0x4803 C088
0x4805 0088
0x4A1A 2088
0x4A1A 8088
0x4A1A E088
RXCLKCHK
Receiver Clock Check
Control
0x4803 808C
0x4803 C08C
0x4805 008C 0x4A1A 208C 0x4A1A 808C
0x4A1A
REVTCTL
Receiver DMA Event Control
E08C
0x4803 80A0
0x4803 C0A0
0x4805 00A0
0x4A1A 20A0 0x4A1A 80A0 0x4A1A E0A0
GBLCTLX
Alias of GBLCTL containing
only transmit reset bits;
allows transmit to be reset
independently from receive
0x4803 80A4
0x4803 C0A4
0x4805 00A4
0x4A1A 20A4 0x4A1A 80A4 0x4A1A E0A4
TXMASK
Transmit Format Unit Bit
Mask
0x4803 80A8
0x4803 C0A8
0x4805 00A8
0x4A1A 20A8 0x4A1A 80A8 0x4A1A E0A8
TXFMT
Transmit Bitstream Format
0x4803 80AC 0x4803 C0AC 0x4805 00AC
0x4A1A
0x4A1A
0x4A1A
TXFMCTL
Transmit Frame Sync Control
20AC
80AC
E0AC
0x4803 80B0
0x4803 C0B0
0x4805 00B0
0x4A1A 20B0 0x4A1A 80B0 0x4A1A E0B0
ACLKXCTL
Transmit Clock Control
0x4803 80B4
0x4803 C0B4
0x4805 00B4
0x4A1A 20B4 0x4A1A 80B4 0x4A1A E0B4
AHCLKXCTL
High Frequency Transmit
Clock Control
0x4803 80B8
0x4803 C0B8
0x4805 00B8
0x4A1A 20B8 0x4A1A 80B8 0x4A1A E0B8
TXTDM
Transmit TDM Slot 0-31
0x4803 80BC 0x4803 C0BC 0x4805 00BC
0x4A1A
0x4A1A
0x4A1A
EVTCTLX
Transmitter Interrupt Control
20BC
80BC
E0BC
0x4803 80C0
0x4803 C0C0
0x4805 00C0 0x4A1A 20C0 0x4A1A 80C0
0x4A1A
TXSTAT
Status Transmitter
E0C0
0x4803 80C4
0x4803 C0C4
0x4805 00C4 0x4A1A 20C4 0x4A1A 80C4
0x4A1A
TXTDMSLOT Current Transmit TDM Slot
E0C4
0x4803 80C8
0x4803 C0C8
0x4805 00C8 0x4A1A 20C8 0x4A1A 80C8
0x4A1A
TXCLKCHK
Transmit Clock Check
E0C8
Control
0x4803 80CC
0x4803
0x4805 00CC
0x4A1A
0x4A1A
0x4A1A
XEVTCTL
Transmitter DMA Control
C0CC
20CC
80CC
E0CC
0x4803 80D0
0x4803 C0D0
0x4805 00D0 0x4A1A 20D0 0x4A1A 80D0
0x4A1A
CLKADJEN
One-shot Clock Adjust
E0D0
Enable
310
Peripheral Information and Timings
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