Z87L01 datasheet(21/51 Pages) ZILOG

21 / 51 page

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

P R E L I M I N A R Y

DS96WRL0800

FUNCTIONAL DESCRIPTION (Continued)

synchronizer, based on detection of a “unique word” fol-

lowing the preamble.

The receiver also features a signal-to-noise ratio detector,

which allows the DSP software to detect noisy channels

and eliminate them from the frequency hopping cycle. The

SNR information is also used by the Z87001 software as a

measure the current range between handset and base sta-

tion. This information allows the adaptive power control al-

gorithm to provide sufficient output power to the RF trans-

mitter.

Receive Frame Counter

The receive frame counter is responsible to keep track of

time within the frame. It is initialized by the frame synchro-

nizer logic on detection of the unique word. It is then

clocked by the recovered bit clock from the bit synchroniz-

er.

On the base station, the receive frame counter is used as

time base for the receiver. On the handset, it is used as

time base for both receiver and transmitter.

Receive Rate Buffer and Voice Interface

The voice signal is generated at the fixed rate of 32 kips by

the Z87010 processor, and transmitted/received in bursts

of 93.09 kips across the air. Data buffers in the transmitter

and receiver are thus necessary to absorb the rate differ-

ences over time. These buffers are called “rate buffers”.

They can store up to 144 data bits and are organized as an

array of 36 4-bit nibbles.

The receive rate buffer stores the received data from the

demodulator. Incoming bits are arranged in 4-bit nibbles

and transferred to successive locations of the rate buffer.

When the last location is reached, transfers resume from

the beginning (circular buffer). The system design guaran-

tees that no buffer overrun nor enduring can occur.

The receive rate buffer can be read by the DSP core pro-

cessor of the Z87001 or by the Z87010 chip. On the

Z87001 side, the buffer can be read as a random-access

memory: the processor writes the nibble address in an ad-

dress register and reads the 4-bit data from a data register.

On the Z87010 side, a voice processor interface logic han-

dles the addressing to automatically present the succes-

sive voice nibbles to the Z87010 in the order they were re-

ceived.

Transmit Rate Buffer and Voice Interface

The transmit rate buffer stores the data to be modulated.

The data is sourced from the Z87010 or the Z87001 core

processor. As for the receive rate buffer, the Z87010 sees

a unique pipe to write to, while the Z87001 DSP core ac-

cesses the rate buffer as random-access memory. The

modulator reads from the rate buffer as from a circular

buffer.

Transmit Frame Timing Counter

On the handset, transmission does not start until the re-

ceiver has synchronized itself to the signal received from

the base station. The transmission timing is based on the

recovered clock. No additional counter is necessary.

On the base station, the situation is different. Transmission

timing is based on a local clock, while the reception’s tim-

ing is based on the clock recovered from the incoming re-

ceived signal. Two counters, respectively clocked by local

and recovered clocks, are necessary to track the transmit

and receive signals.

Note that the receive clock on the base station tracks the

handset’s transmit clock, which is also the handset’s re-

ceive clock and tracks the transmit clock of the base sta-

tion. As a result, receive and transmit clocks of the base

station have exactly the same frequency; only their phases

differ.

Modulator

The modulator consists of a numerically controlled oscilla-

tor (NCO) which generates an FSK (Frequency Shift Key-

ing) signal at the carrier frequency of 2.508 MHz. The car-

rier frequency is shifted plus or minus 32.58 kHz for a “1”

or a “0” data bit. To facilitate conformance to FCC regula-

tions, the transitions from “1” to “0” or vice-versa are

smoothed in order to decrease the amplitude of the side

lobes of the transmit signal. In practice, the jump from one

frequency to the next is performed in several smaller

steps.

The carrier frequency is adjustable by the DSP core pro-

cessor in order to provide additional frequency adjustment

between base and handset. This is provided in case of a

frequency offset too large for possible correction by the

AFC.

The modulator also includes bit inversion logic as dis-

cussed in the receiver section.

Z87L01 Datasheet(PDF) 21 Page - Zilog, Inc.

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