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Z87L01 Datasheet(PDF) 32 Page - Zilog, Inc. |
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Z87L01 Datasheet(HTML) 32 Page - Zilog, Inc. |
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32 / 51 page  Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Zilog 32 P R E L I M I N A R Y DS96WRL0800 ADDITIONAL FEATURES Power Control The Z87001 features several means of measuring and controlling power levels. One input pin (RSSI) connects an external “receive signal strength indicator” to a half flash 8- bit ADC in the Z87001. This ADC is sampled once per frame during the receive portion of the TDD cycle. The RSSI value can be accessed in software in the RSSI_DATA register field. With external multiplexing, the 8-bit ADC can be used for additional purposes. The RSSI data is used by the software to implement adap- tive power control. In order to determine whether the RSSI information is made of signal or noise, the Z87001 includes logic to measure the signal-to-noise ratio (SNR) of the re- ceive signal. This SNR value is available at the end of ev- ery frame in the SNR_ESTIMATE register field. It is also used by the adaptive frequency hopping algorithm to de- termine and avoid the noisy channels. Finally, a 4-bit DAC (resistive ladder) is provided to control RF power output level. The DAC is under software control through register field TX_PWR_DAC_DATA. General-Purpose I/O Ports The Z87001 includes two general-purpose input/output ports, P0 and P1, of 16 bit each. The direction of each bit is independently programmable by setting the register fields DIRECTION0 and DIRECTION1. Then, the software can access the input and output values by accessing DATA0 and DATA1. Two pins of port P1 (pins 14 and 15), when configured in input mode, also behave as interrupt pins for the core pro- cessor. The software can enable or disable each interrupt by setting the INTERRUPT_0_ENABLE and INTERRUPT_2_ENABLE fields. The interrupts are posi- tive edge-triggered. Four pins of port P0 (pins 0 to 3), when configured in input mode, can also be individually programmed as wake-up pins for the Z87001 (See “Sleep mode”, above). Table 7. Data and Control Access to Rate Buffers Field Register Bank Next RX_AUTO_INCREMENT RATE_BUF_ADDR 1 EXT0 RX_BUF_ADDR RATE_BUF_ADDR 1 EXT0 TX_AUTO_INCREMENT RATE_BUF_ADDR 1 EXT0 TX_BUF_ADDR RATE_BUF_ADDR 1 EXT0 RX_BUF_DATA RATE_BUF_DATA 1 EXT0 TX_BUF_DATA RATE_BUF_ADDR 1 EXT1 TX_BUF_DATA RATE_BUF_DATA 1 EXT1 RX_BUF_VP_ADDR RATE_BUF_DATA 1 EXT1 TX_BUF_VP_ADDR RATE_BUF_DATA 1 EXT1 TX_RX_NIBBLE_MARKER RATE_BUF_DATA 1 EXT1 Table 8. Power Control Field Register Bank Ext RSSI_DATA RSSI 2 EXT3 SNR_ESTIMATE RX_CONTROL 2 EXT1 TX_PWR_DAC_DATA CONTROL 1 EXT6 RSSI_DATA RSSI 2 EXT3 SNR_ESTIMATE RX_CONTROL 2 EXT3 Pin Number Interrupt Number DSP Interrupt Vector P1 14 INT0 3FFFh P1 15 INT2 3FFDh Table 9. General-Purpose I/O Ports Field Register Bank Ext DIRECTION0 GPI00DIR 3 EXT4 DATA0 GPI00DATA 3 EXT5 DIRECTION1 GPI0IDIR 3 EXT6 DATA1 GPI0IDATA 3 EXT7 INTERRUPT_0_ENABLE CONTROL 1 EXT6 INTERRUPT_1_ENABLE CONTROL 1 EXT6 |
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