PEB2256HT datasheet(348/490 Pages) INFINEON

348 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

348

2002-08-27

ECM

Error Counter Mode

The function of the error counters (FEC,CEC,CVC,EBC) is

determined by this bit.

= Before reading an error counter the corresponding bit in the

Disable Error Counter register (DEC) has to be set. In 8 bit

access the low byte of the error counter should always be read

before the high byte. The error counters are reset with the rising

edge of the corresponding bits in the DEC register.

1 =

Every

second

the

error

counter

latched

and

then

automatically reset. The latched error counter state should be

read within the next second. Reading the error counter during

updating should be avoided (do not access an error counter

within 1 µs after the one-second interrupt occurs).

SSD0

Select System Date Rate 0

SIC1.SSD1, FMR1.SSD0 and SIC2.SSC2 define the data rate on the

system highway. Programming SSD1/SSD0 and corresponding data

rate is shown below.

SIC2.SSC2 = 0:

00 =

2.048 Mbit/s

01 =

4.096 Mbit/s

10 =

8.192 Mbit/s

11 =

16.384 Mbit/s

SIC2.SSC2 = 1:

00 =

1.544 Mbit/s

01 =

3.088 Mbit/s

10 =

6.176 Mbit/s

11 =

12.352 Mbit/s

XAIS

Transmit AIS Towards Remote End

Sends AIS (blue alarm) on ports XL1, XL2 towards the remote end.

If Local Loop Mode is enabled the transmitted data is looped back to

the system internal highway without any changes.

PEB2256HT Datasheet(PDF) 348 Page - Infineon Technologies AG

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