PEB2256HT datasheet(345/490 Pages) INFINEON

345 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

345

2002-08-27

Single Bit Defect Insertion Register (Read/Write)

Value after reset: 00

After setting the corresponding bit, the selected defect is inserted into the transmit data

stream at the next possible position. After defect insertion is completed, the bit is reset

automatically.

IFASE

Insert single FAS defect

IMFE

Insert single multiframe defect

ICRCE

Insert single CRC defect

ICASE

Insert single CAS defect

IPE

Insert single PRBS defect

IBV

Insert bipolar violation

Note: Except for CRC defects, CRC checksum calculation is done

after defect insertion.

Framer Mode Register 0 (Read/Write)

Value after reset: 00

XC(1:0)

Transmit Code

Serial line code for the transmitter, independent of the receiver.

00 = NRZ (optical interface)

01 = CMI (1T2B+B8ZS), (optical interface)

10 = AMI coding with Zero Code Suppression (ZCS, B7-stuffing).

Disabling of the ZCS is done by activating the clear channel

mode by register CCB(3:1). (ternary or digital interface)

11 = B8ZS Code (ternary or digital dual-rail interface).

After changing XC(1:0), a transmitter software reset is required

(CMDR.XRES = 1).

RC(1:0)

Receive Code

Serial code receiver is independent to the transmitter.

IERR

IFASE

IMFE

ICRCE

ICASE

IPE

IBV

(1B)

FMR0

XC1

XC0

RC1

RC0

FRS

SRAF

EXLS

SIM

(1C)

PEB2256HT Datasheet(PDF) 345 Page - Infineon Technologies AG

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