PEB2256HT datasheet(343/490 Pages) INFINEON

343 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

343

2002-08-27

Transmit Time Slot Register 1 to 4 (Read/Write)

Value after reset: 00

H, 00H, 00H, 00H

TS(31:0)

Transmit Time Slot Register

These bits define the transmit time slots on the system highway to be

inserted. Additionally these registers control the XSIGM marker which

can be forced high during the corresponding time slots independently

of bit CCR1.EITS.

A one in the TTR(4:1) bits inserts the corresponding time slot sourced

by the XFIFO in the data received on pin XDI, if bit CCR1.EITS is set.

If SIC3.TTRF is set and CCR1.EDLX/EITS = 00, insertion of data

received on port XSIG is controlled by this registers.

Assignments:

SIC2.SSC2 = 0: (32 time slots/frame)

TS0

→ time slot 0, TS31 → time slot 31

SIC2.SSC2 = 1: (24 time slots/frame)

TS0

→ time slot 0, TS23 → time slot 23

= The selected time slot is not inserted into the outgoing data

stream.

1 =

The contents of the selected time slot is inserted into the

outgoing data stream from XFIFO. This function is only active,

if bits CCR1.EITS is set.

The corresponding time slot are forced high on marker pin

XSIGM.

TTR1

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

(10)

TTR2

TS8

TS9

TS10

TS11

TS12

TS13

TS14

TS15

(11)

TTR3

TS16

TS17

TS18

TS19

TS20

TS21

TS22

TS23

(12)

TTR4

TS24

TS25

TS26

TS27

TS28

TS29

TS30

TS31

(13)

PEB2256HT Datasheet(PDF) 343 Page - Infineon Technologies AG

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