PEB2256HT datasheet(339/490 Pages) INFINEON

339 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

339

2002-08-27

EITS

Enable Internal Time Slot 0 to 31 Signaling - HDLC Channel 1

0 =

Internal signaling in time slots 0 to 31 defined by registers

RTR(4:1) or TTR(4:1) is disabled.

1 =

Internal signaling in time slots 0 to 31 defined by registers

RTR(4:1) or TTR(4:1) is enabled.

ITF

Interframe Time Fill - HDLC Channel 1

Determines the idle (= no data to be sent) state of the transmit data

coming from the signaling controller.

= Continuous logical 1 is output

= Continuous flag sequences are output (01111110 bit patterns)

XMFA

Transmit Multiframe Aligned - HDLC Channel 1

Determines the synchronization between the framer and the

corresponding signaling controller.

0 =

The contents of the XFIFO is transmitted without multiframe

alignment.

1 =

The contents of the XFIFO is transmitted multiframe aligned.

If CCR1.EDLXis set, transmission of DL-bits is started in F72

format with frame 26. The first byte in XFIFO is transmitted in

the first time slot selected by TTR(4:1) and so on.

After receiving a complete multiframe in the time slot mode

(RTR(4:1)) an ISR0.RME interrupt is generated, if no HDLC or

BOM mode is enabled. In DL-bit access (CCR1.EDLX/

EITS = 10) XMFA is not valid.

Note: During the transmission of the XFIFO content, the SYPX or

XMFS interval time should not be changed, otherwise the

XFIFO data has to be retransmitted.

PEB2256HT Datasheet(PDF) 339 Page - Infineon Technologies AG