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PEB2256HT Datasheet(PDF) 335 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 335 Page - Infineon Technologies AG |
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335 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 335 2002-08-27 Note: During cyclic transmission the XREP-bit has to be set with every write operation to CMDR. XRES Transmitter Reset The transmit framer and transmit line interface excluding the system clock generator and the pulse shaper are reset. However the contents of the control registers is not deleted. XHF Transmit HDLC Frame - HDLC Channel 1 After having written up to 32 bytes to the XFIFO, this command initiates the transmission of a HDLC frame. XTF Transmit Transparent Frame - HDLC Channel 1 Initiates the transmission of a transparent frame without HDLC framing. XME Transmit Message End - HDLC Channel 1 Indicates that the data block written last to the transmit FIFO completes the current frame. The FALC56 can terminate the transmission operation properly by appending the CRC and the closing flag sequence to the data. SRES Signaling Transmitter Reset - HDLC Channel 1 The transmitter of the signaling controller is reset. XFIFO is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. In response to XRES an XPR interrupt is generated. This command can be used by the CPU to abort a frame currently in transmission. Note: The maximum time between writing to the CMDR register and the execution of the command takes 2.5 periods of the current system data rate. Therefore, if the CPU operates with a very high clock rate in comparison with the FALC56's clock, it is recommended that bit SIS.CEC should be checked before writing to the CMDR register to avoid any loss of commands. Note: If SCLKX is used to clock the transmission path, commands to the HDLC transmitter should only be sent while this clock is available. If SCLKX is missing, the command register is blocked after an HDLC command is given. |
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