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PEB2256HT Datasheet(PDF) 336 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 336 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
336
2002-08-27
Mode Register (Read/Write)
Value after reset: 00
H
MDS(2:0)
Mode Select - HDLC Channel 1
The operating mode of the HDLC controller is selected.
000
=Reserved
001
=Signaling System 7 (SS7) support1)
010
=One-byte address comparison mode (RAL1, 2)
011
=Two-byte address comparison mode (RAH1, 2 and RAL1, 2)
100
=No address comparison
101
=One-byte address comparison mode (RAH1, 2)
110
=Reserved
111
=No HDLC framing mode 1
BRAC
BOM Receiver Active - HDLC Channel 1
Switches the BOM receiver to operational or inoperational state.
0
= Receiver inactive
1
= Receiver active
HRAC
Receiver Active - HDLC Channel 1
Switches the HDLC receiver to operational or inoperational state.
0
= Receiver inactive
1
= Receiver active
DIV
Data Inversion - HDLC Channel 1
Setting this bit inverts the internal generated HDLC channel 1 data
stream.
0
= Normal operation, HDLC data stream not inverted
1
= HDLC data stream inverted
70
MODE
MDS2
MDS1
MDS0
BRAC
HRAC
DIV
(03)
1)
CCR2.RADD must be set, if SS7 mode is selected



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