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PEB2256HT Datasheet(PDF) 333 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 333 Page - Infineon Technologies AG |
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333 / 490 page ![]() FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 333 2002-08-27 After reset all control registers except the XFIFO and XS(12:1) are initialized to defined values. Unused bits have to be cleared. 8B CCR3 R/W Common Control Register 3 391 8C CCR4 R/W Common Control Register 4 393 x8D CCR5 R/W Common Control Register 5 394 8E MODE2 R/W Mode Register 2 395 8F MODE3 R/W Mode Register 3 396 92 GCM1 R/W Global Counter Mode 1 397 93 GCM2 R/W Global Counter Mode 2 397 94 GCM3 R/W Global Counter Mode 3 398 95 GCM4 R/W Global Counter Mode 4 399 96 GCM5 R/W Global Counter Mode 5 400 97 GCM6 R/W Global Counter Mode 6 400 9C XFIFO2 W Transmit FIFO 2 402 9D XFIFO2 W Transmit FIFO 2 402 9E XFIFO3 W Transmit FIFO 3 402 9F XFIFO3 W Transmit FIFO 3 402 A0 TSEO R/W Time Slot Even/Odd Select 402 A1 TSBS1 R/W Time Slot Bit Select 1 403 A2 TSBS2 R/W Time Slot Bit Select 2 404 A3 TSBS3 R/W Time Slot Bit Select 3 404 A4 TSS2 R/W Time Slot Select 2 405 A5 TSS3 R/W Time Slot Select 2 405 A8 TPC0 R/W Test Pattern Control Register 0 406 Table 63 T1/J1 Control Register Address Arrangement (cont’d) Address Register Type Comment Page |
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