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PEB2256HT Datasheet(PDF) 338 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 338 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
338
2002-08-27
Interrupt Port Configuration (Read/Write)
Value after reset: 00
H
Unused bits have to be cleared.
SSYF
Select SYNC Frequency
Only applicable in master mode (LIM0.MAS = 1) and bit CMR2.DCF
is cleared.
0
= Reference clock on port SYNC is 1.544/2.048 MHz
(see LIM1.DCOC)
1
= Reference clock on port SYNC is 8 kHz
IC0, IC1
Interrupt Port Configuration
These bits define the function of the interrupt output stage (pin INT):
Common Configuration Register 1 (Read/Write)
Value after reset: 00
H
BRM
BOM Receive Mode - HDLC Channel 1
(significant in BOM mode only)
0
= 10-byte packets
1
= Continuous reception
EDLX
Enable DL-Bit Access through the Transmit FIFO - HDLC
Channel 1
A one in this bit position enables the internal DL-bit access through
the receive/transmit FIFO of the signaling controller. FMR1.EDL has
to be cleared.
70
IPC
SSYF
IC1
IC0
(08)
IC1
IC0
Function
X
0
1
0
1
1
Open drain output
Push/pull output, active low
Push/pull output, active high
70
CCR1
BRM
EDLX
EITS
ITF
XMFA
RFT1
RFT0
(09)



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