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PEB2256HT Datasheet(PDF) 342 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 342 Page - Infineon Technologies AG |
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342 / 490 page ![]() FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 342 2002-08-27 Receive Time Slot Register 1 to 4 (Read/Write) Value after reset: 00 H, 00H, 00H, 00H TS(31:0) Time Slot Register These bits define the received time slots on the system highway port RDO to be extracted. Additionally these registers control the RSIGM marker which can be forced high during the corresponding time slots independently of bit CCR1.EITS. A one in the RTR(4:1) bits samples the corresponding time slot in the RFIFO of the signaling controller, if bit CCR1.EITS is set. Assignments: SIC2.SSC2 = 0: (32 time slots/frame) TS0 → time slot 0,TS31 → time slot 31 SIC2.SSC2 = 1: (24 time slots/frame) TS0 → time slot 0,TS23 → time slot 23 0 = The corresponding time slot is not extracted and stored in the RFIFO. 1 = The contents of the selected time slot is stored in the RFIFO. Although the idle time slots can be selected. This function is only active, if bits CCR1.EITS is set. The corresponding time slot is forced high on pin RSIGM. 70 RTR1 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 (0C) RTR2 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 (0D) RTR3 TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23 (0E) RTR4 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31 (0F) |
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