PEB2256HT datasheet(347/490 Pages) INFINEON

347 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

347

2002-08-27

Framer Mode Register 1 (Read/Write)

Value after reset: 00

CTM

Channel Translation Mode

0 =

Channel translation mode 0

1 =

Channel translation mode 1

The different channel translation modes are described in Table 30 on

page 131.

EDL

Enable DL-Bit Access through Register XDL(3:1)

Only applicable in F4, F24 or F72 frame format.

0 =

Normal operation. The DL-bits are taken from system highway

or if enabled by CCR1.EDLX from the XFIFO of the signaling

controller.

1 =

DL-bit register access. The DL-bit information are taken from

the registers XDL(3:1) and overwrite the DL-bits received on

the system highway (pin XDI) or from the internal XFIFO of the

signaling controller. However, transmission of the contents of

registers XDL(3:1) is disabled if transparent mode is enabled

(FMR4.TM).

PMOD

PCM Mode

For E1 application this bit must be set low. Switching from E1 to T1 or

vice versa the device needs up to 20

µs to settle up to the internal

clocking.

0 =

PCM 30 or E1 mode.

1 =

PCM 24 or T1/J1 mode (see RC0.SJR for T1/J1 selection).

CRC

Enable CRC6

This bit is only significant when using the ESF format.

= CRC6 check/generation disabled. For transmit direction, all

CRC bit positions are set.

= CRC6 check/generation enabled.

FMR1

CTM

EDL

PMOD

CRC

ECM

SSD0

XAIS

(1D)

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