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PEB2256HT Datasheet(PDF) 349 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 349 Page - Infineon Technologies AG |
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349 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 349 2002-08-27 Framer Mode Register 2 (Read/Write) Value after reset: 00 H MCSP Multiple Candidates Synchronization Procedure SSP Select Synchronization/Resynchronization Procedure Together with bit FMR2.SSP the synchronization mode of the receive framer is defined: MCSP/SSP: 00 = F12/F72 format: Specified number of errors in both FT framing and FS framing lead to loss of sync (FRS0.LFA is set). In the case of FS-bit framing errors, bit FRS0.LMFA is set additionally. A complete new synchronization procedure is initiated to regain pulseframe alignment and then multiframe alignment. F24: normal operation: synchronization is achieved only on verification the framing pattern. 01 = F12/F72: Specified number of errors in FT framing has the same effect as above. Specified number of errors in FS framing only initiates a new search for multiframe alignment without influencing pulseframe synchronous state (FRS0.LMFA is set). F24: Synchronous state is reached when three consecutive multiframe pattern are correctly found independent of the occurrence of CRC6 errors. 10 = F12/F24: A one enables a synchronization mode which is able to choose multiple framing pattern candidates step by step. I.e. if in synchronous state the CRC error counter indicates that the synchronization might have been based on an alias framing pattern, setting of FMR0.FRS leads to synchronization on the next candidate available. However, only the previously assumed candidate is discarded in the internal framing pattern memory. The latter procedure can be repeated until the framer locks on the right pattern (no extensive CRC errors). Therefore bit FMR1.CRC must be set. 70 FMR2 MCSP SSP DAIS SAIS PLB AXRA EXZE (1E) |
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