PEB2256HT datasheet(351/490 Pages) INFINEON

351 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

351

2002-08-27

EXZE

Excessive Zeros Detection Enable

Selects error detection mode in the bipolar receive bit stream.

0 =

Only bipolar violations are detected.

1 =

Bipolar violations and zero strings of 8 or more contiguous

zeros in B8ZS code or more than 15 contiguous zeros in AMI

code are detected additionally and counted in the code

violation counter CVC.

LOOP (Read/Write)

Value after reset: 00

RTM

Receive Transparent Mode

Setting this bit disconnects control of the internal elastic store from the

receiver. The elastic store is now in a “free running” mode without any

possibility to actualize the time slot assignment to a new frame

position in case of resynchronization of the receiver. This function can

be used together with the “disable AIS to system interface” feature

(FMR2.DAIS) to realize undisturbed transparent reception.

This bit should be enabled in case of unframed data reception mode.

ECLB

Enable Channel Loop-Back

0 =

Disables the channel loop-back.

1 =

Enables the channel loop-back selected by this register.

Note: CAS-BR must be switched off (FMR5.EIBR = 0) while channel

loop back is enabled.

CLA(4:0)

Channel Address For Loop-Back

CLA = 1 to 24 selects the channel.

During loop-back, the contents of the associated outgoing channel on

ports XL1/XDOP/XOID and XL2/XDON is equal to the idle channel

code programmed in register IDLE.

LOOP

RTM

ECLB

CLA4

CLA3

CLA2

CLA1

CLA0

(1F)

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