PEB2256HT datasheet(354/490 Pages) INFINEON

354 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

354

2002-08-27

Framer Mode Register 5 (Read/Write)

Value after reset: 00

EIBR

Enable Internal Bit Robbing Access

0 =

Normal operation.

1 =

A one in this bit position causes the transmitter to send the bit

robbing signaling information stored in the XS(12:1) (ESF, F12,

72) registers or serial CAS in the corresponding time slots.

XLD

Transmit Line Loop-Back (LLB) Down Code

0 =

Normal operation.

1 =

A one in this bit position causes the transmitter to replace

normal transmit data with the LLB down (deactivate) Code

continuously until this bit is reset. The LLB down code is

overwritten by the framing/DL/CRC bits optionally.

XLU

Transmit LLB Up Code

0 =

Normal operation.

1 =

A one in this bit position causes the transmitter to replace

normal transmit data with the LLB up (activate) code

continuously until this bit is reset. The LLB up code is optionally

overwritten by the framing/DL/CRC bits. For proper operation

bit FMR5.XLD must be cleared.

XTM

Transmit Transparent Mode

0 =Ports SYPX/XMFS define the frame/multiframe begin on the

transmit

system

highway.

The

transmitter

usually

synchronized on this externally sourced frame boundary and

generates the FS/DL-bits according to this framing. Any change

of the transmit time slot assignment subsequently produces a

change of the FS/DL-bit positions.

1 =

Disconnects the control of the transmit system interface from

the transmitter. The transmitter is now in a free running mode

without any possibility to actualize the multiframe position. The

framing (FS/DL-bits) generated by the transmitter are not

“disturbed“ (in case of changing the transmit time slot

assignment) by the transmit system highway unless register

XC1 is written. This bit should be set if loop-timed application is

FMR5

EIBR

XLD

XLU

XTM

SSC2

(21)

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