PEB2256HT datasheet(358/490 Pages) INFINEON

358 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

358

2002-08-27

Release

Depending on the selected multiframe format the alarm is reset when

FALC56 does not detect

– the “bit 2 = 0" condition for three consecutive pulse frames

(all formats if selected),

– the "FS-bit" condition for three consecutive multiframes (F12),

– the "DL pattern" for three times in a row (ESF).

CRCI

Automatic CRC6 Bit Inversion

If set, all CRC bits of one outgoing extended multiframe are inverted

in case a CRC error is flagged for the previous received multiframe.

This function is logically ored with RC0.XCRCI.

XCRCI

Transmit CRC6 Bit Inversion

If set, the CRC bits in the outgoing data stream are inverted before

transmission. This function is logically ored with RC0.CRCI.

RDIS

Receive Data Input Sense

Digital interface, dual-rail:

0 =

Inputs RDIP/RDIN are active low

1 =

Inputs RDIP/RDIN are active high

Digital Interface, CMI:

0 =

Input ROID is active high

1 =

Input ROID is active low

RCO(10:8)

Receive Offset/Receive Frame Marker Offset

Depending on the RP(A to D) pin function different offsets can be

programmed. The SYPR and the RFM pin function cannot be

selected in parallel.

Receive Offset (PC(4:1).RPC(2:0) = 000)

Initial value loaded into the receive bit counter at the trigger edge of

SCLKR when the synchronous pulse on port SYPR is active.

Calculation of delay time T (SCLKR cycles) depends on the value X

of the receive offset register RC(1:0). Refer to register RC1.

PEB2256HT Datasheet(PDF) 358 Page - Infineon Technologies AG

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