PEB2256HT datasheet(362/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

362

2002-08-27

XLT

Transmit Line Tristate

= Normal operation

Transmit line XL1/XL2 or XDOP/XDON are switched into high-

impedance state. If this bit is set the transmit line monitor status

information is frozen (default value after hardware reset).

DAXLT

Disable Automatic Tristating of XL1/2

0 =

Normal operation. If a short is detected on pins XL1/2 the

transmit line monitor sets the XL1/2 outputs into a high-

impedance state.

1 =

If a short is detected on pins XL1/2, the automatic setting of

these pins into a high-impedance state (by the XL-monitor) is

disabled.

Idle Channel Code Register (Read/Write)

Value after reset: 00

IDL(7:0)

Idle Channel Code

If channel loop-back is enabled by programming the register

LOOP.ECLB = 1, the contents of the assigned outgoing channel on

ports XL1/XL2 or XDOP/XDON is set equal to the idle channel code

selected by this register.

Additionally, the specified pattern overwrites the contents of all

channels of the outgoing PCM frame selected by the idle channel

registers ICB(3:1). IDL7 is transmitted first.

Transmit DL-Bit Register 1-3 (Read/Write)

Value after reset: 00

H, 00H, 00H

IDLE

IDL7

IDL0

(2B)

XDL1

XDL17

XDL16

XDL15

XDL14

XDL13

XDL12

XDL11

XDL10

(2C)

XDL2

XDL27

XDL26

XDL25

XDL24

XDL23

XDL22

XDL21

XDL20

(2D)

XDL3

XDL37

XDL36

XDL35

XDL34

XDL33

XDL32

XDL31

XDL30

(2E)

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