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PEB2256HT Datasheet(PDF) 363 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 363 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
363
2002-08-27
XDL(3:1)
Transmit FS/DL-Bit Data
The DL-bit register access is enabled by setting bits FMR1.EDL = 1.
With the transmit multiframe begin an interrupt ISR1.XMB is
generated and the contents of these registers XDL(3:1) is copied into
a shadow register. The contents is subsequently sent out in the data
stream of the next outgoing multiframe if no transparent mode is
enabled. XDL10 is sent out first.
In F4 frame format only XDL10+XDL11 are transmitted. In F24 frame
format XDL10 to 23 are shifted out. In F72 frame format XDL10 to 37
are transmitted.
The transmit multiframe begin interrupt (XMB) requests that these
registers should be serviced. If requests for new information are
ignored, the current contents is repeated.
Clear Channel Register (Read/Write)
Value after reset: 00
H, 00H, 00H
CH(24:1)
Channel Selection Bits
0 =
Normal operation. Bit robbing information and zero code
suppression (ZCS, B7 stuffing) can change contents of the
selected speech/data channel if assigned modes are enabled
by bits FMR5.EIBR and FMR0.XC(1:0).
1 =
Clear channel mode. Contents of selected speech/data
channel are not overwritten by internal or external bit robbing
and ZCS information. Transmission of channel assigned
signaling and control of pulse-density is applied by the user.
70
CCB1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
(2F)
CCB2
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
(30)
CCB3
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
(31)



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