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PEB2256HT Datasheet(PDF) 365 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 365 Page - Infineon Technologies AG |
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365 / 490 page ![]() FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 365 2002-08-27 XDOS Transmit Data Out Sense 0 = Output signals XDOP/XDON are active low. Output XOID is active high (normal operation). 1 = Output signals XDOP/XDON are active high. Output XOID is active low. Note: If CMI coding is selected (FMR0.XC(1:0) = 01) this bit has to be cleared. The transmit frame marker XFM is independent of this bit. EQON Receive Equalizer On 0 = -10 dB receiver: short-haul mode 1 = -36 dB receiver: long-haul mode RLM Receive Line Monitoring 0 = Normal receiver mode 1 = Receiver mode for receive line monitoring; the receiver sensitivity is increased to detect resistively attenuated signals of -20 dB (short-haul mode only) LL Local Loop 0 = Normal operation 1 = Local loop active. The local loop-back mode disconnects the receive lines RL1/RL2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by system interface is routed through the analog receiver back to the system interface. The unipolar bit stream is transmitted undisturbedly on the line. Receiver and transmitter coding must be identical. Operates in analog and digital line interface mode. In analog line interface mode data is transferred through the complete analog receiver. MAS Master Mode 0 = Slave mode 1 = Master mode on. Setting this bit the DCO-R circuitry is frequency synchronized to the clock (1.544, 2.048 MHz or 8 kHz, see IPC.SSYF, LIM1.DCOC) supplied by SYNC. If this pin is connected to V SS or VDD (or left open and pulled up to VDD internally) the DCO-R circuitry is centered and no receive jitter attenuation is performed (only if 1.544 or 2.048 MHz clock is selected by resetting bit IPC.SSYF). The generated clocks are stable. |
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