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PEB2256HT Datasheet(PDF) 364 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 364 Page - Infineon Technologies AG |
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364 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 364 2002-08-27 Idle Channel Register (Read/Write) Value after reset: 00 H, 00H, 00H, 00H IC(24:1) Idle Channel Selection Bits These bits define the channels (time slots) of the outgoing PCM frame to be altered. 0 = Normal operation. 1 = Idle channel mode. The contents of the selected channel is overwritten by the idle channel code defined by register IDLE. Line Interface Mode 0 (Read/Write) Value after reset: 00 H XFB Transmit Full Bauded Mode Only applicable for dual-rail mode (bit LIM1.DRS = 1). 0 = Output signals XDOP/XDON are half bauded (normal operation). 1 = Output signals XDOP/XDON are full bauded. Note: If CMI coding is selected (FMR0.XC(1:0) = 01) this bit has to be cleared. 70 ICB1 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 (32) ICB2 IC9 IC10IC11IC12IC13IC14IC15IC16 (33) ICB3 IC17 IC18 IC19 IC20 IC21 IC22 IC23 IC24 (34) 70 LIM0 XFB XDOS EQON RLM LL MAS (36) |
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