PEB2256HT datasheet(360/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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360 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

360

2002-08-27

Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001

Offset programming of the receive frame marker which is output on

multifunction port RFM. The receive frame marker can be activated

during any bit position of the entire frame and depends on the

selected system clock rate.

Calculation of the value X of the receive offset register RC(1:0)

depends on the bit position which should be marked at marker

position MP:

system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)

≤ MP ≤ 2045:X = MP + 2

2046

≤ MP ≤ 2047:X = MP - 2046)

e.g: 2.048 MHz: MP = 0 to 255; 4.096 MHz: MP = 0 to 511,

8.192 MHz: MP = 0 to 1023, 16.384 MHz: MP = 0 to 2047

system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)

≤ MP ≤ 193 × (SC/SD) - 3:X = MP + 2 + 7 × SC/SD

193

× (SC/SD) -2 ≤ MP ≤ maximum delay:X = MP + 2 - 186 × SC/

with maximum delay = 193

×SC/SD - 1

with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2

with SD = system data rate

PEB2256HT Datasheet(PDF) 360 Page - Infineon Technologies AG